RTL simulation is a core stage in the chip design process that provides key debugging and performance information. However, this process is agonizingly slow and bottlenecks most chip design workloads. Though the code can be broken down into many simple tasks, each task requires large amounts of synchronization to communicate its inputs and outputs to the next module, which negates the benefits of parallelism. ASH proposes a new architecture and compiler to 1) schedule individual tasks as operands become available, and 2) selectively simulate only tasks where inputs have changed, using dataflow execution to reap the full benefits of parallelism.

My first experience with hardware outside of an academic context was writing protocol checkers for ARMÂ’s new cache coherence protocol, and I spent the summer dealing with the bane of every hardware engineerÂ’s existence: RTL simulation times. Working on this SuperUROP is a chance to solve this problem and improve the experience of hardware devs across the board.