The emergence of the network as the bottleneck in the transmission of video content has accelerated the development of more advanced video compression codecs. In turn, these codecs require much more substantial processing power to use, which has led the Digital Integrated Circuits and Systems Group at MIT to develop a High Efficiency Video Coding (HEVC) decoder chip to streamline the process of decoding HD video. This chip is specifically built to decode up to 4Kx2K resolution video while doing so efficiently, consuming only 78mW of power. My research aims to expand the current video system by designing a loop filtering block as part of a new encoder chip. This chip will be used along with an HEVC decoder to demonstrate how the HEVC standard could be used to support high definition video conferencing in an energy efficient manner.

I worked in the Radio Modeling Team at Broadcom in Irvine, CA developing digital models of analog radio circuitry. Previously, I worked in the Visual and Parallel Computing Group at Intel, where I created software to automatize the physical placement and routing of signals in GPUs.