In this project I propose Verik, a Hardware Description Language (HDL) embedded in the Kotlin programming language that seeks to improve the syntax and environment support for SystemVerilog while maintaining its core semantics. It addresses many of the pain points of SystemVerilog by borrowing the type system, dependency resolution mechanism, and IDE support of Kotlin. Verik is compiled to SystemVerilog in a transparent manner and will support both synthesizable and non-synthesizable constructs such as modules, interfaces, and classes. The compiler is implemented as manipulations on a series of syntax trees, with the frontend parser provided by the parser generator ANTLR.

The seeds of this idea originate from work I had done in industry for digital circuit design. There seemed to me a real need to bridge the gap between modern software development methodologies and the current practices in hardware design. I think the problem of finding the most natural mappings for hardware constructs is interesting, and the toolchain that I am building is eminently practical and relevant to work that’ s being done in industry.