MIT EECS — Foxconn Undergraduate Research and Innovation Scholar
RISC-V Processor as a platform for research and education
My research project is to implement a RISC-V processor in Bluespec. RISC-V is a new open instruction set architecture (ISA) developed by UC Berkeley. My aim is to develop different versions of the processor such as in-order core, out-of-order core, super-scalar processor, and to have a stand alone implementation of these processors. These processors will be tested with test suites and will also be able to run Linux.
I worked on RISC-V over this past summer creating a pipelined processor in Bluespec and successfully booted Linux on an FPGA. I hope to further develop this design including creating a out-oforder processor, and in the process gain a deeper understanding in computer architecture. RISC-V is an open ISA intended for research in computer architecture and it is really exciting to be working with this ISA.