MIT EECS - MediaTek Inc Undergraduate Research and Innovation Scholar
Verilog Modeling of Easily Scalable Two-Stage Op-Amp Incorporating Hybrid Miller / Input Feedforward Compensation
Op amps are an important building block for various analog and mixed signal circuits. An opamp topology that has gained interest recently is the two-stage configuration with a hybrid classical Miller/input feed forward compensation.This has been shown to have a very good bandwidth with low power,and is suitable for deep submicron CMOS, low power, low voltage design.Currently, Do Yeon Yoon and Prof. Harry Lee are using this topology in a high bandwidth, low power, DeltaSigma converter design. The goal of this project is to create a Verilog model of this op amp topology that models the characteristics of the topology and contains only a few parameters which can be used to easily scale the gain and phase vs frequency characteristics of the amplifier.
I worked with Prof. Abelson building App Inventor, a web-based graphical tool for creating android apps, followed by work on understanding the behavior of Pentacene-based OFET under high voltage at MIT Microsystems Technology Laboratories. Now, I use signal processing and machine learning techniques to characterize crime scene DNA.