Memory access and communication limit the performance and efficiency of multicore chips as data movement is orders of magnitude more expensive than basic compute operations. To address this problem, our research group has designed an adaptive, reconfigurable cache hierarchy that approaches the performance of application-specific designs, by monitoring application behavior and building a single virtual cache hierarchy suited to its needs. The objective of this SuperUROP project is to enhance this design by building separate instruction and data virtual cache hierarchies. By exploiting these differences between instructions and data needs, we expect the resulting prototype to be helpful for programs with a large instruction footprint, such as server workloads, which are increasingly common.

I have previously worked on HCG-VCSELs as an REU intern at Berkeley with Prof. Chang-Hasnain. Last semester I worked on TaleBlazer at MIT’s STEP lab and interned as an infosec intern at Akamai this summer. I really enjoyed Computation Structures (6.004) and will be taking Constructive Computer Architecture (6.175) this semester. I’m excited to get a chance to apply what I’m learning to my SuperUROP project this year.