Solving sparse systems of linear equations is a crucial component in many science and engineering problems, like simulating physical systems. We present an architecture for accelerating sparse matrix factorization algorithms. However, a specific concern is Network Topology. Chip network topology is the arrangement and organization of interconnects within a chip controlling communication between different parts of the chip, like the processor cores, memory elements, and I/O controllers. The topology determines the pathways for data transmission, affecting the performance, efficiency, latency, and scalability of the chip. We plan on designing and optimizing a network on chip architecture that gets the best performance out of our hardware accelerator for sparse matrix factorization algorithms.

I am participating in this Super-Urop because I think digital systems are really intriguing and I loved optimizing processors in classes like 6.192 (Advanced Computer Architecture) and 6.191 (Computation Structures). I am hoping to gain more experience writing RTL code and designing digital systems from scratch.