Accelerating Super Resolution using Compressed Video
The purpose of my SuperUROP project will be to write an efficient and accurate FPGA infrastructure for ASIC computer vision algorithm accelerators including an existing object detection chip and a planned Simultaneous Localization and Mapping chip. First frames from a stereo camera will be brought into the FPGA system. Some preprocessing including calibration correction and image rectification will be necessary; subsequently the system will perform demosaicing filtering histogram equalization and color balancing. These steps will improve contrast and accurate detection. Processed image pixels will be sent to the ASIC and algorithm outputs will be received. Finally a visualization (such as an overlay with boxes around detected objects) will be output.

This past year I enjoyed taking 6.111 and 6.375 both classes on FPGA design. Through this project I hope to gain more experience with hardware description realizing algorithms in hardware and optimizing digital architectures. I’m also excited to work on computer vision; low-power high-throughput systems like these could open the door to using computer vision for navigation and adaptability in mobile robots.