Dual-rail qubit architectures naturally bias toward erasure errors, which are easier to correct than Pauli errors. A major challenge, however, is the slow speed of erasure detection, which limits the scalability of fault-tolerant protocols. To accelerate erasure checks, we propose an architecture that enhances coupling between qubits and readout ancilla while preserving coherence. We will design native gate sets and erasure check schemes, evaluate robustness under fabrication variances, and benchmark coherence, fidelity, and detection speed. The ultimate goal is a scalable hardware platform enabling faster, lower-overhead quantum error correction.

By participating in SuperUROP, I look forward to engaging in the full research process, particularly presenting and writing papers, while gaining exposure to more advanced research. Building on my prior projects on superconducting qubits in the QCE group, my goal is to produce publication-level research and develop the skills to prepare for a future academic career.