This project aims to prototype computer architecture designs that requires massive SRAM resources using FPGAs, which have abundant SRAM for effective execution of iterative solver algorithms. The focus is on automating the prototyping process, optimizing tile distribution to minimize boards needed and reduce latency, enhancing scalability for varying algorithms, and exploring trade-offs in processing element generality versus resource utilization.

I’m participating in SuperUROP to deepen my understanding of digital system designs, especially FPGAs. Having worked on small FPGA projects, I’m eager to tackle a larger, more complex project to further explore this field.