MIT EECS | Texas Instruments Undergraduate Research and Innovation Scholar
A Hardware Accelerator for Memory-Efficient Irregular Algorithms
- Computer Systems
Irregular algorithms, such as graph analytics and sparse neural networks, are challenging on traditional architectures due to the inherent runtime variations in things such as execution latencies, memory accesses, and branching patterns. While hardware accelerators exist for regular algorithms, for this project, we will design a hardware accelerator for irregular algorithms with more general mechanisms. We could use various tradeoffs between memory and computation, and leverage techniques such as pipeline-level and data-level parallelism to make a better accelerator.
am participating in SuperUROP because I would like to deepen my understanding of computer architecture and how it interacts with algorithms while gaining research experience. I have taken 6.823 (Computer System Architecture) which expanded on my some of the concepts I had learned in 6.004 and piqued my interest in the area. I hope to learn more about research process and deepen my knowledge of computer architecture.