In recent years, many frameworks have been proposed to enable fast design space exploration of deep neural network (DNN) accelerators. However, these frameworks are limited to evaluating accelerator designs supporting single-layer dataflows that serially process each DNN layer. Meanwhile, fused-layer dataflows efficiently reuse output activations stored on-chip by simultaneously processing multiple DNN layers. Thus, fused-layer dataflows can lead to significant reductions in off-chip data transfers, improving bandwidth usage efficiency and thus inference execution time.

To enable modeling of DNN accelerators that support fused-layer dataflows, this paper presents LoopTree. To concisely represent a fused-layer dataflow, LoopTree proposes a representation using a tree of loop nests. In addition, an evaluation framework is also presented. Given an architecture, a workload, and a mapping, LoopTree can generate prediction of important metrics such as latency, energy usage, compute count, memory capacity usage, and memory bandwidth usage.

Through this SuperUROP, I want to gain experience in research in computer architecture. I’ve taken 6.823 (computer systems architecture) and 6.825 (hardware architecture for deep learning) and I want to dive deeper into computer architecture research and its application in deep learning. I also want to learn how to work on a successful research project.