MIT EECS | Hudson River Trading Undergraduate Research and Innovation Scholar
Prefetching in the Swarm Processor
- Software Design and Programming Languages
Multicores provide the opportunity for massive performance gains, however, writing parallel programs often requires explicit synchronization and painful debugging. T4, a compiler targeting the Swarm computer architecture, alleviates these problems with automatic parallelization. T4 divides programs into small tasks, allowing many of these tasks to run in parallel while still producing correct results. My project will focus on implementing prefetching for T4-compiled code. Prefetching is a technique used to hide memory latency by retrieving data from memory and placing that data in the cache before the data is needed by the running program. Accessing cached data is much faster than retrieving the data from memory, so, if timed correctly, prefetching can yield significant performance gains.
I wanted to participate in SuperUROP to explore topics in CS that I’ve become interested in since starting my time at MIT. Through my CS course work, I’ve developed the skills that have prepared me for this project. I hope to learn more about computer architecture and compiler design, and I’m excited to contribute to a project that will enable easier parallelization.