Luo  Qian

Luo Qian

Scholar Title

MIT EECS - Actifio Undergraduate Research and Innovation Scholar

Research Title

Concurrent Skip Quadtrees Using Transactional Memory on Intel(R) Haswell Machines with Transactional Synchronization Extensions




Nir N. Shavit


Recent advances in multicore research has introduced the concept of transactional memory in multicore processes. While software has been able to make transactional memory physically possible, Intel(R) has recently introduced a hardware implementation of transactional memory, called Transactional Synchronization Extensions (TSX), in its line of Haswell machines. With such hardware, transactional memory is much faster now, and we can build correct and efficient concurrent data structures. One such structure of interest is the skip quadtree, which can be applied in many geometric and graphics applications, such as approximate range queries, hit detection of points and objects, etc.


I took my first parallel computing class during my sophomore year in high school, working with POSIX threads and OpenMP in C, and I have since been enamored by its potential. After completing Nir’s 6.836 Multicore Programming course, I became interested in developing common, useful data structures currently nonexistent in parallel frameworks.

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