Graphs are increasingly being applied in machine learning for many domains, such as social network analysis, drug discovery, and financial fraud detection. The need to encode and find complex relationships within large datasets has led to the creation of specialized hardware to better support model-specific algorithm efficiency. However, current hardware accelerators for graph problems are often not scalable and tend to be optimized for a specific algorithm, such as graph random walks. By building on previous work related to a hardware and software co-design for a vector search algorithm, this project aims to design and implement an FPGA-based accelerator for a novel graph-based parallel vector search algorithm and extend the work to more general purpose applicability.

I am participating in SuperUROP because I am interested in gaining in-depth research experience related to high-performance computing architectures for artificial intelligence. I am looking forward to applying the skills I have learned through related coursework and prior research projects.