This project aims to summarize the tradeoffs of superscalar design decisions on RISC-V processors by quantifying the power, performance, and area of implemented processors. The RISC-V processors will differ in the sharing and duplicating of hardware resources, scheduling policy, and the width of the superscalar pipeline. To evaluate these designs, they will all be able to boot Linux and run a suite of benchmarks on FPGA. Area and power will then be evaluated by synthesizing the designs to ASICs. This research will result in an overview of superscalar design and the tradeoffs of various choices. This summary can then be used to introduce students familiar with basic computer architecture to the possibilities offered by superscalar design.

I am participating in SuperUROP to obtain research experience while also gaining a deeper understanding of, and contributing to, the field of computer architecture. In the past, I have taken classes related to architecture, completed a CPU-GPU fluid dynamics UROP, and completed a GPU architecture internship at NVIDIA. I aim to utilize and build upon my experience while also gaining exposure to conducting self-guided research.