This project seeks to address these gaps through the experimental characterization and optimization of highly scaled GaN HEMTs fabricated at MIT.nano, specifically targeting low to medium-voltage (10–100V) applications with an emphasis on high-temperature reliability. The study will systematically investigate the role of passivation layers, field plates, and device geometries in enhancing device performance, leveraging various deposition techniques such as atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), and low-pressure chemical vapor deposition (LPCVD). Key electrical characterization methods will include DC-IV, pulse-IV, Hall effect, transmission line measurements (TLM), capacitance-voltage (C-V), and S-parameter measurements to extract a comprehensive set of physical device parameters.

By participating in this SuperUROP, I hope to gain more experience in modeling and simulations. While I have done a lot of experimental characterization, broadening my knowledge through simulations will help me better understand GaN transistors. I also hope to produce meaningful results that lead to fabricated transistors that replicate the behavior predicted in my simulations.