Chip design is time-consuming and requires lots of expertise in hardware development. Recent advances in LLMs have shown promise in automating code generation, but applying them to hardware design remains challenging. This project explores how LLMs can assist in generating Verilog code and decomposing complex accelerator designs into smaller, verifiable components. By studying existing architectures and evaluating commercial LLMs, the goal is to develop a framework that leverages AI to accelerate and simplify RTL design and verification for hardware accelerators.

My experience taking the digital systems lab (6.205) course sparked my interest in digital circuit design. More specifically, I developed an interest in AI for hardware design at Synopsys, where I worked on a GenAI tool for PPA optimization at the RTL level. Through SuperUROP, I am excited to further explore how LLMs can support Verilog generation and help streamline the chip design process.