MIT EECS - Analog Devices Undergraduate Research and Innovation Scholar
Finding the Speed Limits of an Optical Modulator
Rajeev J. Ram
To further make possible the continuing scaling down in size of the massively multicore processors (continue the Moore’s Law) the processor-to-memory interconnect power consumption must be reduced while increasing the bandwidth. A depletion-mode modulator implemented on a commercial CMOS foundry running a standard 45 nm process has been recently demonstrated. The modulator occupies 80µm2 and operates at 5 Gbps, with 5.2 dB extinction ratio and an approximate energy consumption of 5fJ/ bit. My project will be to further improve this modulator improving the timing while keeping the power consumption low. I will elaborate new designs for the modulator, simulate them using Synopsis tools and when the needed results will be achieved I will continue to the experimental part of the project.
I had experience in physics research (2012-2013) at the Harvard-MIT center for Ultra Cold Atoms under Prof. Ketterle. My sophomore year I was conducting research in the Photonics Microsystem Group under Michael Watts. The classes 6.012, 6.013 have also motivated me for this project.