Strained-Germanium (strained-Ge) channel p-MOSFETs are promising for future high-performance and low-power CMOS technology. Previous studies have shown strained-Ge p-MOSFETs with a thin Si cap demonstrate up to 6.5x hole mobility enhancement, while devices without a Si cap demonstrate a 3x mobility enhancement. However, the details of what contributes to the difference in mobility between these two types of devices require investigation. This work aims to better understand the role of Si cap on hole mobility by characterizing both types of devices at
low temperatures. This work may provide insights for strained-Ge device design for future high-performance and low-power CMOS technology.

I have worked with Professor Tsu Jae King on studying the analog performance of sub-30nm Fully-Depleted SOI MOSFETs as an REU intern at UC Berkeley. I worked with Professor Jesus del Alamo at MIT Microsystems Technology Laboratory (MTL) on studying electron-trapping phenomenon of GaN transistors.