Datalog is a declarative logic programming language with applications in databases and formal verification. While GPU Datalog engines such as GPULog have shown performance gains over CPU-based systems like Souffle, further specialization at the architectural level may yield greater efficiency. This project aims to design a hardware accelerator for Datalog, beginning with a custom processing element for Datalog operations. We then build a software simulator to validate correctness and evaluate throughput. If time permits, this will be followed by an RTL-level implementation in SystemVerilog. We can then test an FPGA implementation of key components to obtain realistic performance results and measure the accelerator’s effectiveness on real-world workloads.

I am participating in SuperUROP to explore high-performance hardware architectures and deepen my research experience. Courses in performance engineering (6.1060), formal verification (6.S057), and FPGAs (6.2050) have prepared me to tackle challenges across the software-hardware stack. I am eager to learn how to conduct long-term research and am most excited by combining rigorous mathematical frameworks with efficient hardware implementations.