As computer chips grow in complexity, simulating their behavior is becoming more costly and, as a result, is taking much longer. The main obstacle to improving the speed of simulating software performance in digital systems is the fact that this simulation cannot be easily parallelized. This project aims to build upon existing techniques and architectures to improve hardware simulation performance through software and hardware optimizations. It will attempt to improve the parallelism capabilities of the software simulator and optimize the simulation to avoid unnecessary work. Another goal involves further specializing the base hardware architecture to exploit more parallelism and increase efficiency. These improvements will be tested on multi-FPGA prototypes to evaluate their performance.

I’m participating in SuperUROP because I’d like to learn more about doing research at the intersection of software and hardware. I have really enjoyed the classes I’ve taken in the basics of computer architecture and systems, and I look forward to being able to apply what I’ ve learned to an active research issue. I am excited to learn more about performance optimization and to see how a team divides and tackles a research goal.