A central challenge when designing CPUs or accelerators is managing the control logic surrounding pipeline hazards. Syncopy is a new HDL that addresses this by decoupling timing-sensitive control logic from functional units and supporting reusable hazard-handling strategies as first-class constructs. Building on this foundation, my research will focus on designing, implementing, and evaluating complex hazard-resolution abstractions in Syncopy that go beyond simple pipelines to support more aggressive microarchitectural features, such as out-of-order execution and shared caches.

During this SuperUROP, I hope to gain a deeper understanding of the complexities behind modern processor and accelerator architecture by automating (in some sense) some of the more complex parts of their design.