Rishab X. Parthasarathy

Rishab X. Parthasarathy

Scholar Title

MIT EECS | Citadel Undergraduate Research and Innovation Scholar

Research Title

An FPGA-Based Spatial Accelerator for Sparse Matrix Operations

Cohort

2024–2025

Department

Electrical Engineering and Computer Science

Research Areas
  • Computer Architecture
Supervisor

Daniel Sanchez

Abstract

While current hardware accelerators, like GPUs, excel on standard matrix operations, they fail to exploit one key matrix property-sparsity-when matrices consist of mostly zeros. One such application of sparsity is reducing the computational cost of solving massive systems of linear equations, which are found in scientific computing from circuits to urban planning. Hence, in this project, our work aims to implement a custom spatial accelerator for solving these sparse linear systems. We will first develop processor elements for sparse matrix-vector multiplies and triangular solves, which will be connected via a custom networking protocol. Then, this system will then be transformed into a real-world implementation on FPGAs, which we will compare to the current state-of-the-art accelerators.

Quote

Through this SuperUROP, I want to gain experience working with practical hardware applications. Drawing from my background in ML and ML Systems, I want to transfer the theoretical knowledge I acquired in Computer Systems Architecture (6.5900) to learn how to build optimized real-world accelerators for scientific computing applications. I’m very excited to expand my knowledge of digital hardware design and hopefully be able to publish my work.

Back to Scholars