Research Project Title:
High Level Synthesis for Highly Parallel Accelerator Architectures
abstract:The Swarm architecture implements hardware task management to apply speculative parallelism and exploit ordered irregular parallelism, with present results showing significant speed-ups. An FPGA implementation currently exists targetting accelerator applications, but this requires the development of specialised hardware processing elements, which is non-trivial and time consuming. We attempt to identify and characterise idiomatic patterns for high level synthesis of algorithms under the SLOT constraints to facilitate efficient PE development with the potential for hardware synthesis directly from sub-tasks automatically extracted from an algorithm by the Swarm compiler.
"Having worked in industry on very high performance heterogeneous computing systems, I am excited to see how the high degree of parallelism available in modern architectures can be exploited to solve the growing number of problems which demand very high computational power. High Level Synthesis is becoming increasingly important in accelerator design, and I am very interested to combine it with the cutting edge research into the Swarm architecture taking place here at MIT."